Senior IC Layout Design Engineer

Vesper

Boston, MA, US
  • Job Type: Full-Time
  • Function: Web/Graphic Design/Internet
  • Industry: Technology
  • Post Date: 10/13/2021
  • Email: jobs@vespermems.com
  • Website: vespermems.com
  • Company Address: 77 Summer Street, Floor 8, Boston, Massachusetts 02110, US

About Vesper

At Vesper, our mission is to deliver voice-powered products to every market, around the world. Our revolutionary piezoelectric mems microphone technology ensures our microphones are immune to dust, water, solder flux vapors and other similar environmental contaminants. As if that weren’t enough, our game-changing zero-power listening technology enables end consumers to have battery-powered devices that can always respond to them. Imagine never having to get up and grab the remote to change the channel, talking to your headphones to switch songs in the middle of an intense workout, or simply having your trash can open without having to put down a heavy load you’re carrying – with Vesper, the possibilities are endless.

Job Description

Vesper is the leader in the high growth MEMS microphone market. Using our cutting-edge proprietary piezoelectric MEMS technology, we have pioneered a new class of voice interface devices. Vesper has a fun and energetic startup culture, and we are well funded by leading VCs such as Accomplice and Amazon’s Alexa Fund, plus we have partnered with leading companies such as DSP Group, Synaptics, GLOBALFOUNDRIES and TSMC.

We are seeking experienced candidates for the role of Senior Layout Design Engineer to join our ASIC team. This is a contract to a hire position.


Responsibilities

The senior layout design engineer will lead the layout design work in the ASIC team, contribute at every level of layout, from transistor level layout of sensitive circuits, to full chip floor planning, top-level interconnects and verification. We design low-noise sensor front-ends, ADCs, power conditioning and more.

Qualifications

Required Qualifications

  • 7+ years of experience in CMOS analog/mixed-signal layout
  • Knowledge of best practice layout techniques for analog circuits. Excellent understanding of device matching and parasitics
  • Experience with integration of block level layouts for ASICs, full chip DRC and LVS and releasing layouts for fabrication
  • Mastery of Cadence Virtuoso Layout XL

Preferred Qualifications

  • Experience with Virtuoso Layout GXL and EXL features
  • Scripting and automation to increase productivity
  • Place and Route of small to medium digital blocks
  • Self-starter with initiative and independent judgment
  • Excellent communication, planning and organizational skills
  • Ability to prioritize and handle multiple tasks at a time

Candidates must be authorized to work in the United States

Wage: This is a contract to a hire position. Vesper offers a competitive salary, benefits and attractive stock option package

Submit CV or resume to:  jobs@vespermems.com

We use cookies to customize your user experience. Click “Agree” if you agree with our Policy.